| 主页 > A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications |
| Published Articles | |
| Title | A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications |
| Related title | A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications |
| Author(s) | Marconi, Sara (Perugia U. ; INFN, Perugia ; CERN) ; Conti, Elia (CERN) ; Placidi, Pisana (Perugia U. ; INFN, Perugia) ; Scorzoni, Andrea (Perugia U. ; INFN, Perugia) ; Christiansen, Jorgen (CERN) ; Hemperek, Tomasz (Bonn U.) |
| Publication | 2017 |
| Number of pages | 7 |
| In: | 2015 Applications in Electronics Pervading Industry, Environment and Society Conference, Rome, Italy, 5 - 6 May 2015, pp.35-41 |
| DOI | 10.1007/978-3-319-47913-2_5 |
| Subject category | Computing and Computers |
| Abstract | The adoption of a system-level simulation environment based on standard methodologies is a valuable solution to handle system complexity and achieve best design optimization. This work is focused on the implementation of such a platform for High Energy Physics (HEP) applications, i.e. for next generation pixel detector readout chips in the framework of the RD53 collaboration. The generic and re-usable environment is capable of verifying different designs in an automated fashion under a wide and flexible stimuli space; it can also be used at different stages of the design process, from initial architecture optimization to final design verification. |