CERN Accelerating science

Article
Report number	arXiv:1709.08303 ; FERMILAB-PUB-17-385-CMS-E-PPD
Title	Performance Study of the First 2-D Prototype of Vertically Integrated Pattern Recognition Associative Memory
Related title	Performance Study of the First 2D Prototype of Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)
Author(s)	Deptuch, Gregory (Fermilab) ; Hoff, James (Fermilab) ; Jindariani, Sergo (Fermilab) ; Liu, Tiehui (Fermilab) ; Olsen, Jamieson (Fermilab) ; Tran, Nhan (Fermilab) ; Joshi, Siddhartha (Northwestern U.) ; Li, Dawei (Northwestern U.) ; Ogrenci-Memik, Seda (Northwestern U.)
Publication	2020-01-22
Imprint	2017-09-24
Number of pages	8
In:	IEEE Trans. Nucl. Sci. 67 (2020) 2111-2118
In:	21st IEEE Real Time Conference, Williamsburg, Va, United States Of America, 9 - 15 Jun 2018, pp.2111-2118
DOI	10.1109/TNS.2020.2968860
Subject category	hep-ex ; Particle Physics - Experiment ; physics.ins-det ; Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; CMS CERN HL-LHC
Abstract	Extremely fast pattern recognition capabilities are necessary to find and fit billions of tracks at the hardware trigger level produced every second anticipated at high luminosity LHC (HL-LHC) running conditions. Associative Memory (AM) based approaches for fast pattern recognition have been proposed as a potential solution to the tracking trigger. However, at the HL-LHC, there is much less time available and speed performance must be improved over previous systems while maintaining a comparable number of patterns. The Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) Project aims to achieve the target pattern density and performance goal using 3DIC technology. The first step taken in the VIPRAM work was the development of a 2D prototype (protoVIPRAM00) in which the associative memory building blocks were designed to be compatible with the 3D integration. In this paper, we present the results from extensive performance studies of the protoVIPRAM00 chip in both realistic HL-LHC and extreme conditions. Results indicate that the chip operates at the design frequency of 100 MHz with perfect correctness in realistic conditions and conclude that the building blocks are ready for 3D stacking. We also present performance boundary characterization of the chip under extreme conditions.
Copyright/License	preprint: (License: arXiv nonexclusive-distrib. 1.0) publication: © 2020 IEEE

Corresponding record in: Inspire