002265892 001__ 2265892
002265892 003__ SzGeCERN
002265892 005__ 20191015172322.0
002265892 0247_ $$2DOI$$a10.22323/1.282.0912
002265892 0248_ $$aoai:inspirehep.net:1596793$$pcerncds:CERN:FULLTEXT$$pcerncds:FULLTEXT$$pcerncds:CERN$$qINSPIRE:HEP$$qForCDS
002265892 035__ $$9http://inspirehep.net/oai2d$$aoai:inspirehep.net:1596793$$d2017-05-24T17:57:07Z$$h2017-05-25T04:40:51Z$$mmarcxml
002265892 035__ $$9Inspire$$a1596793
002265892 041__ $$aeng
002265892 100__ $$aSteffen, [email protected]$$uTech. U., Munich (main)$$uCERN
002265892 245__ $$aOverview and Future Developments of the intelligent, FPGA-based DAQ (iFDAQ) of COMPASS
002265892 260__ $$bSISSA$$c2016
002265892 300__ $$a4 p
002265892 520__ $$9PoS$$aModern experiments in high energy physics impose great demands on reliability, efficiency, and data rate of Data Acquisition Systems (DAQ). In order to address these needs, we present a versa- tile and scalable DAQ which executes the event building task entirely in FPGA modules. In 2014, the intelligent FPGA-based DAQ (iFDAQ) was deployed at the COMPASS experiment located at the Super Proton Synchrotron (SPS) at CERN. The core of the iFDAQ is its hardware Event Builder (EB), which consists of up to nine custom designed FPGA modules complying with the μ TCA/AMC standard. The EB replaced 30 distributed online computers and around 100 PCI cards increasing compactness, scalability, reliability, and bandwidth compared to the previous system. The iFDAQ in the configuration of COMPASS provides a bandwidth of up to 500 MB/s of sustained rate. By buffering data on different levels, the system exploits the spill structure of the SPS beam and averages the maximum on-spill data rate of 1.5 GB/s over the whole SPS duty cycle. It can even handle peak data rates of 8 GB/s. Its Run Control Configuration and Readout (RCCAR) software offers native user-friendly control and monitoring tools and together with the firmware of the modules provides built-in intelligence like self-diagnostics, data consis- tency checks, and front-end error handling. From 2017, all involved point-to-point high-speed links between front-end electronics, the hardware EB, and the readout computers will be wired via a passive programmable crosspoint switch. Thus, multiple event building topologies can be configured to adapt to different system sizes and communication patterns.
002265892 540__ $$3publication$$aCC-BY-NC-SA$$bSISSA
002265892 65017 $$2SzGeCERN$$aDetectors and Experimental Techniques
002265892 65017 $$2SzGeCERN$$aComputing and Computers
002265892 690C_ $$aCERN
002265892 693__ $$aCERN SPS$$eNA58
002265892 700__ $$aBai, Yunpeng$$uTech. U., Munich (main)
002265892 700__ $$aBodlak, Martin$$uCTU, Prague
002265892 700__ $$aFrolov, Vladimir$$uDubna, JINR
002265892 700__ $$aHuber, Stefan$$uTech. U., Munich (main)
002265892 700__ $$aJary, Vladimir$$uCTU, Prague
002265892 700__ $$aKonorov, Igor$$iINSPIRE-00399564$$uTech. U., Munich (main)
002265892 700__ $$aLevit, Dmytro$$uTech. U., Munich (main)
002265892 700__ $$aNovy, Josef$$uCTU, Prague
002265892 700__ $$aSubrt, Ondrej$$uCTU, Prague$$uCERN
002265892 700__ $$aVirius, Miroslav$$uCTU, Prague
002265892 773__ $$c912$$pPoS$$vICHEP2016$$wC16-08-03$$y2016
002265892 8564_ $$uhttps://pos.sissa.it/archive/conferences/282/912/ICHEP2016_912.pdf$$yPoS server
002265892 8564_ $$81315786$$s551119$$uhttps://cds.cern.ch/record/2265892/files/PoS(ICHEP2016)912.pdf$$yFulltext
002265892 960__ $$a13
002265892 962__ $$b2005743$$k912$$nchicago20160803
002265892 980__ $$aARTICLE
002265892 980__ $$aConferencePaper
002265892 999C6 $$a0-1-0-2-0-0-1$$t2017-04-27 10:06:54$$vInvenio/1.1.2.1260-aa76f refextract/1.5.44$$vcontent.pdf;1