CERN Accelerating science

CMS Note
Report number	CMS-CR-2017-034
Title	Performance of the CMS Event Builder
Author(s)	Andre, Jean-Marc Olivier (Fermilab) ; Behrens, Ulf (DESY) ; Branson, James (UC, San Diego) ; Brummer, Philipp Maximilian (CERN) ; Chaze, Olivier (CERN) ; Cittolin, Sergio (UC, San Diego) ; Contescu, Cristian (Fermilab) ; Craigs, Benjamin Gordon (CERN) ; Darlea, Georgiana Lavinia (MIT) ; Deldicque, Christian (CERN) ; Demiragli, Zeynep (MIT) ; Dobson, Marc (CERN) ; Doualot, Nicolas (Fermilab) ; Erhan, Samim (UCLA) ; Fulcher, Jonathan Richard (CERN) ; Gigi, Dominique (CERN) ; Gladki, Maciej Szymon (CERN) ; Glege, Frank (CERN) ; Gomez Ceballos, Guillelmo (MIT) ; Hegeman, Jeroen Guido (CERN) ; Holzner, Andre Georg (UC, San Diego) ; Janulis, Mindaugas (Vilnius U.) ; Jimenez Estupinan, Raul (Zurich, ETH) ; Masetti, Lorenzo (CERN) ; Meijers, Franciscus (CERN) ; Meschi, Emilio (CERN) ; Mommsen, Remigius (Fermilab) ; Morovic, Srecko (Fermilab) ; O'Dell, Vivian (Fermilab) ; Orsini, Luciano (CERN) ; Paus, Christoph Maria Ernst (MIT) ; Petrova, Petia (ISER, Sofia ; CERN) ; Pieri, Marco (UC, San Diego) ; Racz, Attila (CERN) ; Reis, Thomas (CERN) ; Sakulin, Hannes (CERN) ; Schwick, Christoph (CERN) ; Simelevicius, Dainius (Vilnius U.) ; Zejdl, Petr (Fermilab)
Publication	2017
Imprint	13 Feb 2017
Number of pages	8
In:	J. Phys.: Conf. Ser. 898 (2017) 032020
In:	22nd International Conference on Computing in High Energy and Nuclear Physics, CHEP 2016, San Francisco, Usa, 10 - 14 Oct 2016, pp.032020
DOI	10.1088/1742-6596/898/3/032020
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; CMS
Abstract	The data acquisition system (DAQ) of the CMS experiment at the CERN Large Hadron Collider assembles events at a rate of 100 kHz, transporting event data at an aggregate throughput of to the high-level trigger farm. The DAQ architecture is based on state-of-the-art network technologies for the event building. For the data concentration, 10/40 Gbit/s Ethernet technologies are used together with a reduced TCP/IP protocol implemented in FPGA for a reliable transport between custom electronics and commercial computing hardware. A 56 Gbit/s Infiniband FDR Clos network has been chosen for the event builder. This paper presents the implementation and performance of the event-building system.
Copyright/License	publication: (License: CC-BY-3.0)

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