CERN Accelerating science

Published Articles
Report number	AIDA-PUB-2013-017
Title	Prototype of a gigabit data transmitter in 65 nm CMOS for DEPFET pixel detectors at Belle-II
Author(s)	Kishishita, T (UBONN) ; Krüger, H (UBONN) ; Hemperek, T (UBONN) ; Lemarenko, M (UBONN) ; Koch, M (UBONN) ; Gronewald, M (UBONN) ; Wermes, N (UBONN)
Publication	2013
Imprint	2013-08-01
In:	Nucl. Instrum. Methods Phys. Res., A 718 (2013) pp.168-172
Subject category	Detectors and Experimental Techniques ; 3: Microelectronics and interconnection technology ; 3.3: Shareable IP Blocks for HEP
Abstract	This paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via 40 cm Kapton flex and 12–15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output data stream from an 80 cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25 ps (1s distribution) by connecting the chip with 38 cm flex and 10 m TWP cables.

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