CERN Accelerating science

ATLAS Note
Report number	ATL-DAQ-PROC-2014-030
Title	ATLAS FTK challenge: simulation of a billion-fold hardware parallelism
Author(s)	Adelman, J (Nothern Illinois U.) ; Ancu, L S (Geneva U.) ; Annovi, A (INFN, Frascati) ; Baines, J (Rutherford) ; Britzger, D (DESY) ; Ehrenfeld, W (Bonn U.) ; Giannetti, P (INFN, Pisa) ; Luongo, C (INFN, Pisa) ; Schmitt, S (DESY) ; Stewart, G (Glasgow U.) ; Tompkins, L (Stanford U.) ; Vaniachine, A (Argonne) ; Volpi, G (Pisa U.)
Corporate Author(s)	The ATLAS collaboration
Publication	2014
Imprint	02 Oct 2014
Number of pages	5
In:	16th International workshop on Advanced Computing and Analysis Techniques in physics (ACAT), Prague, Czech Republic, 1 - 5 Sep 2014
Subject category	Particle Physics - Experiment
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Abstract	During the current LHC shutdown period the ATLAS experiment will upgrade the Trigger and Data Acquisition system to include a hardware tracker coprocessor: the Fast TracKer (FTK). The FTK receives data from the 80 million of channels of the ATLAS silicon detector, identifying charged tracks and reconstructing their parameters at a rate of up to 100 KHz and within 100 microseconds. To achieve this performance, the FTK system identifies candidate tracks utilizing the computing power of a custom ASIC chip with associative memory (AM) designed to perform “pattern matching” at very high speed; track parameters are then calculated using modern FPGAs. A detailed simulation of this massive system has been developed with the goal of supporting the hardware design and studying its impact in the ATLAS online event selection at high LHC luminosities. We present the issues related to emulating this system on a general-purpose CPU platform, using ATLAS computing Grid resources, and the solutions developed in order to mitigate these problems and allow the studies required to support the system design, construction and installation.
Copyright/License	Preprint: (License: CC-BY-4.0)