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From: bakul@netcom.com (Bakul Shah)
Subject: Re: On-the-fly code generation
Message-ID: <bakulD6Jw4w.A7y@netcom.com>
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References: <bakulD69s9w.44D@netcom.com> <3lh3nm$l6t@bell.maths.tcd.ie> <3ljaih$h29@info.epfl.ch> <3lra5o$bv6@goanna.cs.rmit.edu.au>
Date: Wed, 5 Apr 1995 07:14:56 GMT
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>"Stefan Monnier" <monnier@di.epfl.ch> writes:
>>I can see the problem with split caches, and I admit it can get a tiny bit more
>>annoying with multi-level caches (even though it generally doesn't since only
>>the first level is split), but what does the pipeline depth has to do with RTCG?

ok@goanna.cs.rmit.edu.au (Richard A. O'Keefe) writes:
>What happens if you store new code into a location which has _already_
>been fetched into the pipeline?

You can usually abstract out system dependent issues like this
into a separate `kiss-of-life' procedure that converts generated
code data into executable code.  So in that sense kiss-of-life
details have nothing to do with RTCG.

>With deep pipelines (11 stages have been mentioned recently in comp.arch)
>plus branch target caches (like on older ADM 29ks) or other branch
>prediction schemes, even branches won't save you.

AMD 29000 would've complicated things further as it had separate
data and instruction busses and on some systems address N fetched
you different things depending whether it was an instn access or
data access.  On some systems you would have to copy from data
memory to instn memory via an *external* DMA device or something
- *if* you could do so at all (but remember that such systems
were _not_ designed for RTCG!).

But Amd29k is not alone in this respect.  There are probably
hundreds of different N-deep-pipeline/branch target
cache/speculative execution/split-cache etc. combinations in
use.  Probably best to hide details of how this is done in a
separate procedure (which may also involve an OS call or two, if
the cache flushing is only available in the supervisor mode).

Bakul Shah <bakul@netcom.com>
