| Article | |
| Title | Intelligent trigger processor for the crystal box |
| Author(s) | Sanders, G H ; Butler, H S ; Cooper, M D ; Hart, G W ; Hoffman, C M ; Hogan, G E ; Hughes, E B ; Matis, H S ; Rolfe, J ; Sandberg, V D ; Williams, R A ; Wilson, S ; Zeman, H |
| Affiliation | (Los Alamos Nat Lab, Los Alamos, NM, USA) |
| Publication | CERN, 1981 |
| In: | Topical Conference on the Application of Microprocessors to High-energy Physics Experiments, pp.214-229 |
| DOI | 10.5170/CERN-1981-007.214 |
| Subject category | Nuclear Physics |
| Abstract | A large solid angle angular modular NaI(Tl) detector with 432 phototubes and 88 trigger scintillators is being used to search simultaneously for three lepton flavor-changing decays of the muon. A beam of up to 10/sup 6/ muons stopping per second with a 6% duty factor would yield up to 1000 triggers per second from random triple coincidences. A reduction of the trigger rate to 10 Hz is required from a hardwired primary trigger processor. Further reduction to <1 Hz is achieved by a microprocessor-based secondary trigger processor. The primary trigger hardware imposes voter coincidence logic, stringent timing requirements, and a non-adjacency requirement in the trigger scintillators defined by hardwired circuits. Sophisticated geometric requirements are imposed by a PROM-based matrix logic, and energy and vector-momentum cuts are imposed by a hardwired processor using LSI flash ADC's and digital arithmetic logic. The secondary trigger employs four satellite microprocessors to do a sparse data scan, multiplex the data acquisition channels and apply additional event filtering. (9 refs). |
Record created 2005-08-03, last modified 2019-02-21
