CERN Accelerating science

ATLAS Note
Report number	ATL-ELEC-PUB-2007-004 ; ATL-COM-ELEC-2005-001
Title	TTC Interface Module for ATLAS Read-Out Electronics : Final production version based on Xilinx FPGA devices
Author(s)	Butterworth, J (University Coll. London) ; Lane, J B (University Coll. London) ; Postranecky, M (University Coll. London) ; Warren, M R M (University Coll. London)
Publication	CERN, 2004
Imprint	13 Sep 2004
Number of pages	5
In:	10th Workshop on Electronics for LHC and Future Experiments, pp.320-324
DOI	10.5170/CERN-2004-010.320
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Free keywords	TIM ; SCT ; TTC ; Interface ; ROD
Abstract	The functionality and the details of firmware, software and hardware of the Xilinx FPGA-based production version of the ATLAS-SCT TTC Interface Module ( TIM ) are described. The TIM interfaces to the ATLAS Level-1 Trigger, using the LHC-standard TTC ( Timing, Trigger and Control ) system. Twelve prototype TIM modules have been built and used since 2001, based around ten AMD/Lattice CPLD devices. Final production modules, based on two Xilinx FPGAs, are all being built this year. The details of the hardware and firmware transition from CPLD to FPGA version are described, including the use of new software tools.
Copyright/License	Preprint: (License: CC-BY-4.0)

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