CERN Accelerating science

ATLAS Note
Report number	ATL-DAQ-CONF-2005-002 ; ATL-COM-DAQ-2004-030
Title	Irradiation tests of ROHM 0.35um ASIC and Actel Anti-fuse FPGA for the ATLAS Muon Endcap Level-1 Trigger System
Author(s)	Ichimiya, R (Kobe U.) ; Tsuji, S (Kobe U.) ; Arai, Y (KEK, Tsukuba) ; Ikeno, M (KEK, Tsukuba) ; Sasaki, O (KEK, Tsukuba) ; Ohshita, H (Shinshu U.) ; Takada, N (Shinshu U.) ; Hane, Y (Tokyo U., ICEPP) ; Hasuko, K (Tokyo U., ICEPP) ; Nomoto, H (Tokyo U., ICEPP) ; Sakamoto, H (Tokyo U., ICEPP) ; Shibuya, K (Tokyo U., ICEPP) ; Takemoto, T (Tokyo U., ICEPP) ; Fukunaga, C (Tokyo Metropolitan U.) ; Toshima, K (Tokyo Metropolitan U.) ; Sakuma, T (Tokyo U. of Agric. Tech.)
Publication	CERN, 2004
Number of pages	5
In:	10th Workshop on Electronics for LHC and Future Experiments, pp.117-121
DOI	10.5170/CERN-2004-010.117
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Free keywords	trigger ; radiation damage ; FPGA ; ASIC
Abstract	In order to implement a level-1 trigger logic in an efficient manner from timing and space consumption point of view, application specific IC chips (ASIC) as well as FPGA ones are vitally used in the ATLAS muon end-cap level-1 trigger system. Various subsidiary logics are implemented in FPGAs while the core trigger logic is implemented in ASICs. These components will suffer for ten years the radiation of approximately 100Gy of total ionizing dose (TID) and a hadron fluence of 2x10^10hadrons/cm^2, which will cause single event upset (SEU) or single event latch up (SEL). We intend to use Rohm 0.35um gate width CMOS technology for ASIC and Actel anti-fuse based FPGA. In this presentation we report the result of irradiation test of devices made with these technologies and discuss validity of them to use in the system.
Copyright/License	Preprint: (License: CC-BY-4.0)

Corresponding record in: Inspire