CERN Accelerating science

ATLAS Note
Report number	ATL-DAQ-PROC-2022-020
Title	Integration of FPGA RDMA into the ATLAS Readout with FELIX in High Luminosity LHC
Author(s)	Vasile, Matei (Horia Hulubei National Institute of Physics and Nuclear Engineering (RO)) (+) ; Martoiu, Sorin (Horia Hulubei National Institute of Physics and Nuclear Engineering (RO)) (+) ; Boukadida, Nayib (Nikhef National institute for subatomic physics (NL)) (+) ; Stoicea, Gabriel (Horia Hulubei National Institute of Physics and Nuclear Engineering (RO)) (+) ; Micu, Petru (University Politehnica of Bucharest (RO)) (+) ; Dumitru, Alexandru (University Politehnica of Bucharest (RO)) (+) ; Ulmamei, Andrei-Alexandru (University Politehnica of Bucharest (RO)) (+) ; Hobincu, Radu (University Politehnica of Bucharest (RO)) (+) ; Iordache, Cristina-Cerasela (University Politehnica of Bucharest (RO)) (+)
Corporate Author(s)	The ATLAS collaboration
Collaboration	ATLAS Collaboration
Publication	2023
Imprint	21 Oct 2022
Number of pages	5
In:	JINST 18 (2023) C01025
In:	Topical Workshop on Electronics for Particle Physics 2022 (TWEPP 2022), Bergen, Norway, 19 - 23 Sep 2022, pp.C01025
DOI	10.1088/1748-0221/18/01/C01025
Subject category	Particle Physics - Experiment
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Free keywords	FPGA ; RDMA ; FELIX ; TDAQ
Abstract	The FELIX system is used to interface the front-end electronics and the commodity hardware in the server farm. FELIX is using RDMA through RoCE to transmit data from its host servers to the Software Readout Driver using off-the-shelf networking equipment. In the current version of FELIX, RDMA communication is implemented using software on both ends of the links. Improvements of the data throughput as part of the High Luminosity LHC upgrade, by implementing RDMA support in the front-end FELIX FPGA, have been tested. Now, a version of FELIX that uses the FPGA implementation of RDMA is being proposed and demonstrated.

Corresponding record in: Inspire