CERN Accelerating science

ATLAS Note
Report number	ATL-DAQ-PROC-2022-009
Title	Software based readout driver evolution towards 1 MHz readout as part of the ATLAS HL-LHC upgrade
Author(s)	Kolos, Serguei (University of California Irvine (US)) ; ATLAS TDAQ Collaboration
Corporate Author(s)	The ATLAS collaboration
Collaboration	ATLAS Collaboration
Publication	2022
Imprint	20 Aug 2022
Number of pages	4
In:	23rd IEEE Real Time Conference (RT2022), Online, 1 - 5 Aug 2022
Subject category	Particle Physics - Experiment
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Free keywords	Data acquisition ; Object oriented programming
Abstract	The High-Luminosity Large Hadron Collider (HL-LHC), which should begin operation in 2029, aims to increase LHC luminosity by a factor of 10 beyond its original design. In preparation for this increase, the ATLAS experiment has planned a major upgrade program that is split into two steps. During the “Phase-I” step, that will be completed in 2022, several new trigger and detector systems have been introduced and a new software application, called Software Readout Driver (SW ROD) developed to read data from these new systems. The SW ROD receives and aggregates data from the detector front-end electronics via the Front-End Link eXchange (FELIX) system. For LHC Run 3, which begins in 2022, the SW ROD will be used in parallel with the legacy Readout System (ROS), both operating at an input rate of 100 kHz. For the ‘Phase-II’ upgrade step, to be completed after Run 3 in time for Run 4 in 2029, the legacy ROS will be completely replaced with a new system based on the next generation of FELIX and a new software application called the Data Handler. The Data Handler is an evolution of the SW ROD that has the same functional requirements but must be able to operate at an input rate of 1 MHz. This contribution describes the design and implementation of the SW ROD application for Run 3. It also presents and discusses the results of performance measurements which demonstrate that the SW ROD application already fulfils the Phase-II performance requirements by being able to process data at a 1 MHz rate for realistic Phase-II input configurations.