Author(s)
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Nodari, Benedetta (IP2I, Lyon) ; Bergamin, Gianmario (CERN) ; Caponetto, Luigi (Lyon, IPN) ; Caratelli, Alessandro (CERN) ; Ceresa, Davide (CERN) ; De Clercq, Jarne Theo (Vrije U., Brussels) ; Galbit, Geoffrey Christian (Lyon, IPN) ; Jain, Sandhya (Louvain U.) ; Kloukinas, Konstantinos (CERN) ; Scarfi', Simone (CERN) ; Seif El Nasr, Sarah (Bristol U.) ; Viret, Sebastien (Lyon, IPN) |
Abstract
| The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase 2 CMS Outer Tracker at the High-Luminosity LHC (HL-LHC). Prototyped in a 65 nm CMOS technology, the CIC aggregates the digital data coming from eight upstream front-end chips, formatting it into data packets containing the trigger information from eight bunch crossings and the raw data from events passing the Level 1 (L1) trigger, before transmission to the lpGBT. The role of the CIC in the readout chain is to provide an extra factor of data reduction by grouping data over time and space. A first prototype, the CIC1, integrating all functionalities for system level operation, has been tested in early 2019. A brief description of the functionalities and the test results obtained concerning the performance characterization and the radiation tolerance of the chip are presented in this contribution. |