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Title	Design and simulation of a 65 nm Macro-Pixel Readout ASIC (MPA) for the Pixel-Strip (PS) module of the CMS Outer Tracker detector at the HL-LHC
Author(s)	Ceresa, Davide (CERN) ; Caratelli, Alessandro (Ecole Polytechnique, Lausanne ; CERN) ; Kaplon, Jan (CERN) ; Kloukinas, Kostas (CERN) ; Murdzek, Jan (CERN) ; Scarfi, Simone (CERN ; Ecole Polytechnique, Lausanne)
Publication	SISSA, 2017
Number of pages	5
In:	PoS TWEPP-17 (2017) 032
In:	Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.032
DOI	10.22323/1.313.0032
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; CMS
Abstract	The MPA is the pixel readout ASIC for the hybrid Pixel-Strip module of the Phase-II CMS Outer Tracker upgrade at the High Luminosity LHC (HL-LHC). It employs a novel technique for identifying high transverse momentum particles and provides this information at 40 $MHz$ rate to the L1-trigger system. The chip also comprises a binary pipeline buffer for the L1-trigger latency, and a data path to support the readout of full events with a maximum trigger rate of 1 $MHz$ and a latency of 12.8 $\mu s$. The design and implementation in a 65 $nm$ CMOS technology of the first prototype ASIC that integrates all functionalities for system level operation with a power density lower than 90 $mW/cm^2$ are presented in this contribution.
Copyright/License	Copyright owned by the author(s) publication: (License: CC-BY-NC-ND-4.0)

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