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Abstract
| A DAQ system is developed within the SiW-Ecal ILC collaboration. It provides a flexible and scalable architecture, compound of four parts. A detector interface (DIF) extracting data from front-end electronics and sending them as packets. Two levels of data concentration, control clock and fast command fanout. The two cards, named DCC and GDCC, use respectively FastEthernet and GigaEthernet. A software suite (named Calicoes) allows to control the DAQ and the detector chips and to acquire data from GigaEthernet. It also includes programs for decoding frontend readout to various formats, and also dispatching and aggregating data. Overall architecture, performance in test beam and prospects for use with hundreds of thousands channels are discussed. |