CERN Accelerating science

Preprint
Report number	AIDA-CONF-2014-008
Title	Tests of the First Three-Dimensionally Integrated
Author(s)	Maj, P (AGH-UST, Cracow) ; Carini, G (SLAC) ; Deptuch, G (Fermilab) ; Grybos, P (AGH-UST, Cracow) ; Kmon, P (AGH-UST, Cracow) ; Siddons, D P (Brookhaven) ; Szczygiel, R (AGH-UST, Cracow) ; Trimpl, M (Fermilab) ; Yarema, R (Fermilab)
Publication	2014
Imprint	2012-09-21
Presented at	Vertex 2012, Jeju, Republic Of Korea, 16 - 21 Sep 2012
Subject category	Detectors and Experimental Techniques ; 3: Microelectronics and interconnection technology ; 3.2: 3D Interconnection
Abstract	We report on the results from testing of the first three-dimensionally integrated readout chip for pixel detectors, which application is in X-ray Photon Correlation Spectroscopy (XPCS) experiments on light sources. The chip was designed in the 130nm Tezzaron/GF process as a two-tier device with effectively 12 metal layers of routing. It counts about 1,700 transistors in total in 80x80um^2 pixels. The chip explores broadly the benefits of the 3D integration for pixel detectors, like full separation of analog and digital parts by placing them accordingly on distinct tiers, improved power distribution by using back-side located pads and almost no periphery for achieving 4-side buttability. VIPIC1, as that is the name of the chip, was designed by FNAL in collaboration with AGH-UST. The tests are underway on the singulated devices from the first successfully bonded wafer pairs. Correct operation of all components tested so far was observed. This includes: full sparsified readout that is based on a priority encoder, pipelined inpixel hit acquisition with two alternately switched event counters, programming interfaces for permanent setting and disabling of a pixel and acquisition of hits from the analog part with full sensitivity to settings of discriminator thresholds. Current work is focused on measurements of pixel-to-pixel deterministic offsets, electronic noise and calibration of gain using injection of test charges. Every pixel features multiple connections across two-tier boundary. No faults were observed in the 3D bonding interface as well as the connectivity carried by through silicon vias was observed to be achieved on all dies that were qualified as good after wafer thinning. Despite of the long waiting for the first 3D chips, the test results are encouraging for the threedimensional integration technology as a cost and performance efficient alternative to the aggressive node down scaling.
Submitted by	[email protected]