| ATLAS Note | |
| Report number | ATL-TILECAL-PROC-2013-017 |
| Title | Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench |
| Author(s) |
Carrio, F (Valencia U., IFIC) ; Kim, H Y (Texas U., Arlington) ; Moreno, P (Witwatersrand U.) ; Reed, R (Witwatersrand U.) ; Sandrock, C (Witwatersrand U.) ; Shalyugin, A (Dubna, JINR) ; Schettino, V (Juiz de Fora U.) ; Souza, J (Juiz de Fora U.) ; Solans, C (CERN) ; Usai, G (Texas U., Arlington) ; Valero, A (Valencia U., IFIC) |
| Publication | 2014 |
| Imprint | 12 Nov 2013 |
| Number of pages | 11 |
| In: | JINST 9 (2014) C03023 |
| In: | Topical Workshop on Electronics for Particle Physics, Perugia, Italy, 23 - 27 Sep 2013, pp.C03023 |
| DOI | 10.1088/1748-0221/9/03/C03023 |
| Subject category | Detectors and Experimental Techniques |
| Accelerator/Facility, Experiment | CERN LHC ; ATLAS |
| Free keywords | LHC; ATLAS; Tile Calorimeter; Maintenance; FPGA; Embedded system; PowerPC; IP Core; Embedded Linux |
| Abstract | The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (LS1) improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities as TTCvi emulation, G-Link decoder ADC control and data reception, needed to perform the desired tests |
| Copyright/License | publication: © 2014-2025 CERN (License: CC-BY-3.0) |
Corresponding record in: INSPIRE
Registro creado el 2013-11-12, última modificación el 2022-08-10
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